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TA1395FNG TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC
TA1395FNG
Mixer/Oscillator and PLL IC for TV/VCR Tuner
The TA1395FNG is a tuner IC for TV and VCR applications that integrates a PLL block and mixer, oscillator and IF amplifier on a single chip. The control data of the PLL block conforms to IC-bus formats. Small flat package: SSOP24 (0.65 mm pitch)
Features
Vcc: 5V typ. Two-band mixer Two-band oscillator IF output driver Asymmetrical IF output IC bus format control 33-V high voltage tuning amplifier built-in Three-bit bandswitch drive transistor Frequency steps: 31.25 kHz, 50 kHz, 62.5 kHz (when a 4 MHz crystal is used) Four-programmable chip address Power on reset circuit Automatic changeover between 1/4 and 1/2 prescaler through data input Standby mode Package: Pb-free
Weight: 0.09 g (typ.)
Power on reset status
Frequency step: 62.5 kHz Charge pump current: Low Counter data: ALL [ 0 ] Band driver: OFF Tuning amplifier: OFF (charge pump is sink mode) Local oscillator and mixer: UHF mode
note1: This device is easy to be damaged by high voltage or electric fields. In regards to this, please handle with care. note2: Install the product correctly. Otherwise, it may result in break down, damage and/or degration to the product or equipment.
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TA1395FNG Block Diagram
24
23
22
21
20
19
18
17
16
15
Charge Pump
14
13
Reference Divider
1/2 1/4
1/32 1/33
Programmable Divider
Phase Comparator
POR Band Driver ADR
Data Interface
Band SW Lock
1
2
3
4
5
6
7
8
9
10
11
12
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes.
Terminal Name
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UHF RF input VHF RF input GND 1 Mixer output 1 Mixer output 2 IF AMP input Band output port : BS_V Band output port : BS_VH Band output port : BS_FM ADR (address setting) SDA in/output SCL input GND 2 Crystal input NF Vt output IF output Vcc GND 3 UHF oscillator 1 UHF oscillator 2 VHF oscillator -C1 VHF oscillator -C2 VHF oscillator -B1 Pin Name
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TA1395FNG Terminal Function
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. Pin No. Pin Name. Function Interface
1
RF signal input pin for the UHF band. 1 UHF RF Input Asymmetrical input type
GND
2
RF signal input pin for the VHF band. 2 VHF RF Input Asymmetrical input type
GND
3
GND 1
Ground pin
Mixer output pins 4 Mixer Output 5 A tank circuit is connected between the pins for tuning. Since these are open collector outputs, be sure to connect with a power supply through a load (resistance, coil).
4 5
6
IF AMP input pin 6 IF Amp Input This pin and a pin4 are connected through a capacity.
GND
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TA1395FNG
Pin No. Pin Name. Function Interface
Vcc
7 8 9
BS_V BS_VH BS_FM
The output port of the band block can be set up using the bandswitch data. Bear in mind that drive current differs according to each band drive port.
50k
7 8 9
DATA I/F
GND
Vcc
150k 100k 1k
Address setting pin 10 ADR The address of the PLL block is set up using the voltage applied to this pin.
10
100
50k
GND
Vcc
11
SDA
Serial data input and output pin
11
22
1k
70k
GND
Vcc
12
SCL
Serial clock input pin
12
1k
GND
13
GND 2
Ground pin
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TA1395FNG
Pin No. Pin Name. Function Interface
Vcc 14
Crystal oscillator input pin. 14 Crystal Input A 4-MHz crystal is used.
GND
Vcc
15 NF Be sure to connect a resistance (of about 33 k ) between pin 16 and the 33-V external power supply for tuning. To prevent abnormal oscillation, connect between pin 16 and GND a capacity element that does not affect a PLL. 16 Vt Output
50 16
50
50
GND 15
Vcc
IF signal output pin 17 IF Output Asymmetrical output type. Output impedance is about 75 .
17
GND
18
Vcc
Power supply pin
19
GND 3
Ground pin
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TA1395FNG
Pin No. Pin Name. Function Interface
20
21
20 UHF Oscillator 21
Local oscillator for the UHF band The oscillator type is symmetrical amplifier.
GND
23
22
22 23 24 VHF Oscillator
Local oscillator for the VHF band The oscillator type is symmetrical amplifier.
24
GND
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TA1395FNG Maximum Ratings
CHARACTERISTIC Vcc Tuning Amplifier Voltage Applied Input terminal voltage Power Dissipation Operating Temperature Junction Temperature Storage Temperature PIN No 18 16

SYMBOL Vcc VBT VIN PD Topr Tj Tstg
RATING 6 38 GND-0.3~Vcc+0.3 890 (note4) -20~85 150 -55~150
UNIT V V V mW
-
note3: The absolute maximum ratings of a semiconductor device are a set of specified parameter values that must not beexceeded during operation, even for an instant. If any of these rating are exceeded during operation, the electrical characteristics of the device may be irreparably altered, in which case the reliability and lifetime of the device can no longer be guaranteed. Moreover, any exceeding of the ratings during operation may cause breakdown, damage and/or degradation in other equipment. Applications using the device should be designed so that no maximum rating will ever be exceeded under any operating conditions. Before using, creating and/or producing designs, refer to and comply with the precautions and conditions set forth in this documents. note4: 50 x 50 x 1.6 mm, Cu 40% board used. When using the device at above Ta = 25 by 7.2 mW for each increase of 1 . , decrease the power dissipation
Operating Supply Voltage
Pin No. 18 SYMBOL Vcc MIN. 4.5 TYP. 5.0 MAX. 5.5 UNIT V
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TA1395FNG Electric Characteristics
(Unless otherwise specified, Vcc = 5 V, Ta = 25 )
CHARACTERISTICS SYMBOL Icc-1 Power Supply and Current Icc-2 Icc-3 1 TEST BAND CIRCUIT VHF UHF VHF Conversion Gain (see 1) VHF CG 2 UHF UHF VHF IF Output Power Level (see 2) VHF Ifp 2 UHF UHF VHF Conversion Gain Shift (see 3) VHF CGs 2 UHF UHF Band Port Drive Current BS_V IBD-V 1 Charge Pump Output Current Ichg 1 ACK Output Voltage VACK 1 CP = 1 Isink = 3 mA 190 250 310 0.4 V RF = 373.25 MHz -35 dBmWin RF = 801.25 MHz -35 dBmWin Pin 7, maximum drive current RF = 373.25 MHz RF = 801.25 MHz RF = 55.25 MHz -35 dBmWin RF = 367.25 MHz -35 dBmWin 8.5 8.5 0.3 1 1024 - 0.3 2.7 - 20 - 10 40 11.0 11.0 0.15 2 55 0.5 0.5 0.5 0.5 5 mA dB RF = 373.25 MHz -40 dBmWin RF = 801.25 MHz -40 dBmWin RF = 55.25 MHz RF = 367.25 MHz 26 27 8.5 8.5 29 30 11.0 11.0 32 33 dBmW TEST CONDITION (note5, 6) B1 = ON (BS_VH=open) B3 = ON (BS_FM=open) Power Save setting RF = 55.25 MHz -40 dBmWin RF = 367.25 MHz -40 dBmWin MIN. 52 53 6 21 22 TYP. 65 66 9 24 25 MAX. 78 79 12 27 28 dB mA UNIT
Band Port Drive Current BS_VH Band Port Drive Current BS_FM Band Port Drive Maximum Current Band Port Drive Voltage Drop Tuning Amplifier Output Voltage (Close Loop) Tuning Amplifier Maximum Current Crystal Negative Resistance Ratio Setting Range Logic Input Low Voltage Logic Input High Voltage Logic Input Current (Low) Logic Input Current (High)
IBD-VH IBD-FM IBD-MAX VBDsat Vt out Ivt XtR N VBsL VBsH I BsL I BsH
1 1 1 1 1 1 1 1 1 1 1
Pin 8, maximum drive current Pin 9, maximum drive current Maximum drive current / 2 port ON With each port at maximum current drive. 1 port ON Isink = 1.5 mA VBT = 33 V 4-MHz crystal used 15-bit counter SDA, SCL pin SDA, SCL pin SDA, SCL pin SDA, SCL pin CP = 0
10 5 15 0.2 33 1.5 32767 1.5 Vcc +0.3 10 20 70
mA mA mA V V mA k Ratio V V A A A
note5: IF output frequency: 45.75 MHz
note6: IF output load: 75
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TA1395FNG Reference Data
(Unless otherwise specified, Vcc = 5 V, Ta = 25 ) This data is a reference value and is not guaranteed.
CHARACTERISTICS SYMBOL TEST CIRCUIT BAND VHF Noise Figure (see 4) VHF NF 2, 3 UHF UHF VHF Frequency Shift (The PLL is not operating.) (see 5) VHF fB 2 UHF UHF VHF Switch On Drift (The PLL is not operating.) (see 6) VHF fs 2 UHF UHF VHF 1% Cross Modulation (see 7) VHF CM 2, 4 UHF UHF VHF C / S Beat (see 8) VHF IM3 2, 4 UHF UHF Ch5 Ch Beat (see 9) Ch6 chA-5 RF Input Maximum Level Without Lock-out Crystal External Input Minimum Level Crystal External Input Maximum Level Crystal External Input Frequency VHF RF-in 2 UHF Xo extl-l Xo extl-h Xo extf 1 1 1 Pin 1 4-MHz signal input 4-MHz signal input D / U is above 10dB 300 2, 4 VHF fd = 373.25 MHz, -10dBmWout fd = 801.25 MHz, -10dBmWout fp = 77.25MHz, fud = 83.25MHz Lo = 123MHz fp = 83.25MHz, fud = 87.75MHz Lo = 129MHz fp = 91.25MHz Lo = 137MHz Pin 2 65 65 62 66 65 70 70 67 71 70 fd = 373.25 MHz, -40dBmWin fd = 801.25 MHz, -40dBmWin fd = 55.25 MHz, -10dBmWout fd = 367.25 MHz, -10dBmWout - 30 - 31 65 65 - 26 - 27 70 70 OSC = 419 MHz OSC = 847 MHz fd = 55.25 MHz, -40dBmWin fd = 367.25 MHz, -40dBmWin OSC = 419 MHz OSC = 847 MHz OSC = 101 MHz OSC = 413 MHz RF = 373.25 MHz, DSB RF = 801.25 MHz, DSB OSC = 101 MHz OSC = 413 MHz TEST CONDITION (note5,6) RF = 55.25 MHz, DSB RF = 367.25 MHz, DSB MIN. TYP. 12.0 11.0 8.5 9.0 MAX. 14.0 13.0 dB 10.5 11.0 50 200 kHz 150 700 250 1350 kHz 450 1550 UNIT

- 25 - 28

- 21 - 24

10 dBmW dBc dBc dBmW

4
650
mVp-p mVp-p MHz

note5: IF output frequency: 45.75 MHz
note6: IF output load: 75
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TA1395FNG IC Bus Line Characteristic
CHARACTERISTICS SCL Clock Frequency Bus Free Time between a STOP and a START Condition Hold Time (Repeated) START Condition Low Period of the SCL Clock High Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Rise Time of both SDA and SCL Signal Fall Time of both SDA and SCL Signals Set up Time for STOP Condition SYMBOL fscl tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tsU;STO TEST CONDITION MIN. 0 1.3 0.6 1.3 0.6 0.6 0 100 0.6 TYP. MAX. 400 0.9 300 300 UNIT kHz
s s s s s s s s s s
SDA tBUF tLOW tR tF tHD; STA
SCL
P
S
tHD; STA
tHD; DAT
tHIGH
tSU; DAT
tSU; STA Sr
tSU; STO
P
Figure 1:
IC-bus data timing chart (falling edge timing)
Timing charts may be simplified for explanatory purposes.
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TA1395FNG Test Conditions
Conversion Gain (see 1) RF Input level = -40dBmW (untuned) IF Output Power Level (see 2) Measure IF output level when it is maximum level. Conversion Gain Shift (see 3) The conversion gain shift is defined as a change in conversion gain when supply voltage varies from Vcc = 5 V to 4.5 V or from Vcc = 5 V to 5.5 V. Noise Figure (see 4) Noise figure meter used. Direct reading. (DSB) Frequency Shift (the PLL is not operating) (see 5) The frequency shift is defined as a change in oscillator frequency when supply voltage varies from Vcc = 5 V to 4.5 V or from Vcc = 5 V to 5.5 V. Switch On Drift (the PLL is not operating) (see 6) It is frequency change of oscillator by three minutes on the basis of the three seconds back of an after a power supply. 1% Cross Modulation (see 7) fd = fp : (fd input level = -40dBmW) fud = fp 12MHz, 100 kHz AM30% Input two signals, and increase the fud input level. Measure the fud input level when the suppression level reaches 56.5dB. C/S Beat (see 8) fp fs = fp + 4.5MHz fc = fp + 3.58MHz fp = fs = fc : 3 signal are same level input Measure the suppression level when the PIF(45.75MHz) level is -10dBmW output. Ch Beat (see 9) *Ch5 beat fp = 77.25MHz fud = 83.25MHz Lo = 123MHz tuning Beat frequency = fud 2 - Lo = 43.5MHz fp = fud : 2 signal are same level input Measure the suppression level when the PIF(45.75MHz) level is -10dBmW output. *Ch6 beat fp = 83.25MHz fs = 87.75MHz Lo = 129MHz tuning Beat frequency = fp + fs - Lo = 42MHz fp = fs : 2 signal are same level input Measure the suppression level when the PIF(45.75MHz) level is -10dBmW output. *ChA-5 beat fp = 91.25MHz Lo = 137MHz tuning Beat frequency = Lo - fp 2 = 45.5MHz Measure the suppression level when the PIF(45.75MHz) level is -10dBmW output.
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TA1395FNG Description of PLL Block Operation
- IC bus control The TA1395FNG conforms to the IC-bus format. IC-bus mode enables two-way bus communications with Write Mode, which receives data, and Read Mode, which sends data. Write Mode and Read Mode are set using the last bit (R/W bit) of the address byte. If the last address bit is set to [0], Write Mode is selected; if it is set to [1], Read Mode is selected. Addresses can be set using the hardware bits, and four programmable addresses are available. With this setting, multiple frequency synthesizers can be used in the same IC-bus. The address for the hardware bit setting can be selected by applying voltage to the address setting pin (ADR: pin 10).An address is selected according to the set bits. If the correct address bytes are received, the serial data (SDA) line is "Low" during acknowledgment; when Write Mode is set, the serial data (SDA) line is "Low" during the next acknowledgment if the data byte is programmed. The IC is equipped with 1/2 and 1/4 built-in prescalers, and it is possible to change from one prescaler to the other using input data. When a frequency step of 62.5 kHz is selected, the 1/2 prescaler operates with a divider ratio of 1024 to 4095, and the 1/4 prescaler operates with a divider ratio of 4096 to 32767. When the frequency step selected is 31.25 kHz and 50 kHz, the 1/2 prescaler operates with a divider ratio of 1024 to 8191, and the 1/4 prescaler operates with a divider ratio of 8192 to 32767. In addition, even if the prescaler is changed, the data is calculated in the internal circuit and is processed so that the comparison frequency in each the frequency step does not change. For a frequency step of 62.5 kHz: 15.625 kHz comparison frequency For a frequency step of 50 kHz: 12.5 kHz comparison frequency For a frequency step of 31.25 kHz: 7.8125 kHz comparison frequency This IC incorporates a built-in power-on reset circuit for which a detection voltage of approximately 1.4 V has been set. When the Vcc is supplied, a delay or stoppage in a power supply voltage close to this detection voltage may cause the power-on reset circuit to malfunction, in which case there is a risk that some data may not be received even after the recommended voltage has been restored.
A) Write Mode (Setting Command)
When WRITE mode is set so that the different types of information may be received, byte 1 is used to specify the address data; byte 2 and byte 3, the frequency data; byte 4, function setting data such as the divider ratio setting; and byte 5, the output port data (bandswitch data). Data are latched and transferred one after the other in the case of byte 3, byte 4 and byte 5, while byte 2 and byte 3 are latched and transferred as a two-byte set (byte 2 + byte 3). Once a correct address is received and acknowledged, the data type is determined by whether the first bit of the next byte is set to [0] or [1]. [0] indicates frequency data, while [1] indicates function setting or output data. Until the IC-bus STOP CONDITION is detected, the additional data can be input without transmitting the address data again. (For example: Frequency sweep is possible with additional frequency data.) If data transmission is aborted, data programmed before the abort are valid.
BYTE 1
Hardware bit setting of byte 1 is possible using the address data. The hardware bit is set with the voltage applied to the address-setting pin (ADR: pin 10).
BYTE 2, BYTE 3
Byte 2 , byte 3 are stored in the 15-bit shift register with counter data for the frequency setting, and control the 15-bit programmable counter ratio. The program frequency can be calculated in the following formula: fosc = 4 x fr x N. fosc 4 fr N : Program frequency : Prescaler : Phase comparator reference frequency : Counter total divider ratio
fr is calculated using the crystal oscillator and the reference frequency divider ratio set in byte 4 (control byte): fr = crystal oscillator frequency / reference divider ratio. The reference frequency divider ratio can be set to 1/512, 1/320, and 1/256. When using a 4-MHz crystal oscillator, fr = 7.8125 kHz, 12.5 kHz, and 15.625 kHz. The step frequency is 31.25 kHz, 50.0 kHz, and 62.5 kHz.
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TA1395FNG BYTE 4
Byte 4 is a control byte used to set the different functions. Bit 2 (CP) and controls the output current of the charge-pump circuit. When bit 2 is set to [0], the output current is set to +55 A; when it is set to [1] , it is +250 A. Bit 3 (T2), bit 4 (T1), and bit 5 (T0) are used to set charge pump, the phase comparator reference signal output and counter divider output in test mode. (For details of test mode, see the test mode setting table.) Bit 6 (Rsa) and bit 7 (Rsb) are used to set the crystal reference frequency divider ratio. (For details of the crystal reference frequency divider ratio, see the table for crystal reference frequency divider ratios.) Bit 8 (OS) is used to set the charge-pump driver amplifier output setting. When bit 8 is set to [0], the output is ON (the normal setting used); when it is set to [1], the output is OFF (charge pump is sink mode).
BYTE 5
Byte 5 is used to set the test mode and control the output ports (BS_V, BS_VH, BS_FM). When a bandswitch data is set to [0], the output port is OFF; when it is set to [1], it is ON. Bandswitch setting is also used to switch between the VHF and UHF bands and it is control standby mode. When the bandswitch data for either B1 or B2 is [1], VHF mode is effective. When the bandswitch data for both B1 and B2 is [0], UHF mode is effective. When the bandswitch data for both B1 and B2 is [1], Standby mode is effective. Set the following maximum values for currents to the bandswitch driver. Ensure also that the total band current is within 15 mA when two bands are operating at the same time. BS_V (pin 7) output current: 5 mA (maximum) BS_VH (pin 8) output current: 10 mA (maximum) BS_FM (pin 9) output current: 5 mA (maximum)
B) READ MODE (Status Request)
When Read Mode is set, power-on reset operation status and phase comparator lock detector output status are output to the master device. Bit 1 (POR) indicates the power-on reset operation status. When the power supply of Vcc stops, this bit is set to [1]. The conditions for reset to [0] are that voltage supplied to Vcc is 3V or higher, that transmission is requested in READ MODE, and that the status is output. (When Vcc is turned on, bit 1 is also set to [1].) Bit 2 (FL) indicates the phase comparator lock status. When this is locked, [1] is output; when it is unlocked, [0] is output.
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TA1395FNG DATA FORMAT A) WRITE MODE
MSB 1 2 3 4 5 Address Byte Divider Byte 1 Divider Byte 2 Control Byte Band SW Byte 1 0 N7 1 X 1 N14 N6 CP X 0 N13 N5 T2 X 0 N12 N4 T1 X 0 N11 N3 T0 X MA1 N10 N2 Rsa B3 MA0 N9 N1 Rsb B2 LSB R/W = 0 N8 N0 OS B1 ACK ACK ACK (L) ACK (L) ACK (L)
X :DON'T CARE ACK :Acknowledged (L) :Latch and transfer timing
B) READ MODE
MSB 1 2 Address Byte Status Byte 1 POR 1 FL 0 1 0 1 0 1 MA1 1 MA0 1 LSB R/W=1 1 ACK -
ACK :Acknowledged
DATA SPECIFICATIONS
MA1, MA0 : programmable hardware address bits MA1 0 0 1 1 MA0 0 1 0 1 ADDRESS PIN APPLIED VOLTAGE 0 to 0.1Vcc OPEN or 0.2Vcc to 0.3Vcc 0.4Vcc to 0.6Vcc 0.9Vcc to Vcc
N14 - N0 : programmable counter data CP : charge pump output current setting [0] : + 55 A (typ.) [1] : + 250 A (typ.) T2, T1, T0 : test mode setting bits CHARACTERISTIC Normal operation OFF Charge-pump SINK SOURCE Reference signal output 1/2 counter divider output T2 0 0 1 0 1 1 T1 0 1 1 1 0 0 T0 X 0 0 1 0 1 Charge pump is OFF Only charge pump sink current is ON Only charge pump source current is ON Reference signal output 1/2 counter output X note7: Testing of the counter divider output requires the input of programmable counter data. NOTE (check output: NF) (check output: NF) (check output: NF) (check output: BS_FM) (check output: BS_V) :DON'T CARE
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TA1395FNG
Rsa, Rsb: Reference frequency divider ratio select bit. Rsa 1 0 X Rsb 1 1 1 DIVIDER RATIO 1/256 1/512 1/320 COMPARE FREQUENCY 15.265kHz 7.8125kHz 12.5kHz STEP FREQUENCY 62.5kHz 31.25kHz 50kHz
OS: tuning amplifier control bit [0] : tuning amplifier ON (normal operation) [1] : tuning amplifier OFF (charge pump is sink mode) B3, B2, B1: Band output port control and band change control bit The Bandswitch data controls band port, mixer and oscillator, standby mode. When the standby mode set, it is operating only bus-inter-face and crystal oscillator. B2, B1 data
Bandswitch Data B2 0 0 1 1 B1 0 1 0 1 Band Output Port BS_V (pin7) OFF ON ON OFF BS_VH (pin8) OFF OFF ON OFF Operation Mixer, Oscillator - UHF VHF VHF OFF (Standby Mode)
B3 data
Bandswitch Data B3 0 1 Band Output Port BS_FM (pin9) OFF ON Operation Mixer, Oscillator - Not relation Not relation
POR: power-on reset flag [0] : normal operation [1] : reset operation FL: lock detect flag [0] : unlocked [1] : locked X : don't care
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TA1395FNG -EXAMPLE OF BUS DATA TRANSMITTERS: Start ADR: Address Byte DIV1: Divider Byte 1 (frequency data) DIV2: Divider Byte 2 (frequency data) CONT: Control Byte BAND: Bandswitch Byte A: Acknowledge P: Stop [1] Transmitter - 1 S ADR
A
DIV1
A
DIV2
A
CONT
A
BAND
A
P
[2] Transmitter - 2 S ADR
A
CONT
A
BAND
A
DIV1
A
DIV2
A
P
[3] Transmitter - 3 (This can be applied if control data and bandswitch data have already been programmed.) S ADR A DIV1 A DIV2 A P
[4] Transmitter - 4 (This can be applied if frequency data have already been programmed.) S ADR A CONT A BAND A P
[5] Transmitter - 5 (This can be applied if frequency counter data and bandswitch data have already been programmed.) S ADR A CONT A P Until the IC-bus STOP condition is detected, it is possible to input the additional data without transmitting the address data again. (For example: Frequency sweep is possible with additional frequency data.) If data transmission is aborted, data programmed before the abort are valid.
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TA1395FNG TEST CIRCUIT 1
Vcc(5V)
Icc
51 1000pF 0.1uF
*X'tal
Xo extl
NF
0.1uF
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
24
23
22
21
20
19
18
17
16
15
Charge Pump
14
18pF
XtR
13
Reference Divider
1/2 1/4
1/32 1/33
Programmable Divider
Phase Comparator
POR Band Driver ADR
Data Interface
Band SW Lock
1
2200pF
2
2200pF
3
4
5
0.01uF
6
7
8
9
10
11
12
100
ADR VBDsat IBD
SDA
SCL
note8: Components in the test circuits are only used to obtain and confirm the device characteristics. These components and circuits do not warrant to prevent the application equipment from malfunction or failure.
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100
TA1395FNG TEST CIRCUIT 2
2200pF
2200pF
VH
1.5k
VL
1.5k
33k 0.01uF 33k
33k
Vt(33V)
56pF 33k
1SS241 2200pF 2200pF 2.7k 22k Vcc(5V) L4 1SV262 1000pF 33k 1SV262 10pF 5pF 5pF 82pF 10pF 10pF 7pF L3 10pF 0.1uF
L2
L1
IF out 2200pF 20k
24
23
22
21
20
19
18
17
16
100pF
15
Charge Pump
0.047uF
33
18pF *X'tal
2200pF
14
13
Reference Divider
1/2 1/4
1/32 1/33
Programmable Divider
Phase Comparator
POR Band Driver ADR
Data Interface
Band SW Lock
1
2200pF 2200pF
2
3
4
1.2k L5 33pF
5
0.01uF
6
7
8
9
10
11
12
100
33pF
BS_V
BS_VH BS_FM ADR SDA SCL
note8: Components in the test circuits are only used to obtain and confirm the device characteristics. These components and circuits do not warrant to prevent the application equipment from malfunction or failure.
L1 : 0.4mmd, 2.5mm, 6.5t L2 : 0.4mmd, 2.5mm, 2.5t L3 : 0.4mmd, 2.5mm, 2.5t L4 : 0.4mmd, 1.5mm, 1.5t L5 : Toko (886BNF-0357) X'tal : 4MHz (NDK; AT-51) *IF output pin is 75 load.
Measurement bus data setting Charge pump: High [250 A (typ.)] Frequency step: 62.5 kHz
100
UHF in
VHF in
1000pF
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100
TA1395FNG TEST CIRCUIT 3
Noise Figure Meter out 1 or 2 DUT Noise Source 17 75-50 Impedance Transformer in
Figure 2: Noise Figure measurement
TEST CIRCUIT 4
Signal Generator 1 Signal Generator 3 1 or 2 DUT 17 75-50 Impedance transformer in Spectrum Analyzer
Signal Generator 2
Figure 3: 1%Cross Modulation _ C/S beat _ Ch beat measurement
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TA1395FNG I2C BUS CONTROL SUMMARY Data transmission format
S Slave address 7 bit MSB MSB 0A Data 8 bit MSB A Data 8 bit AP
S: Start condition P: Stop condition A: Acknowledge (1) Start / stop conditions
Serial data
Serial clock S Start condition P Stop condition
(2)
Bit transfer
Serial data
Serial clock
Serial data unchanged. Serial data can be changed.
(3)
Acknowledge
High impedance
Serial data from master device Serial data from slave device Serial clock from master device High impedance
S
1
8
9
(4)
Slave address
A6 1
A5 1
A4 0
A3 0
A2 0
A1 *
A0 *
R/W 0
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TA1395FNG OUTLINE DRAWING
Weight: 0.09 g (typ.)
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TA1395FNG HANDLING PRECAUTIONS
1. Using a human charge model (C=100pF, R=1.5k , test repeated three times), the product's electrostatic resistance was determined to be low in the following cases. (1) When a positive voltage is applied across pin1(UHF RF input) and Vcc and any GND. (2) When a positive voltage is applied across pin2(VHF RF input) and any GND. (3) When a positive voltage is applied across pin16(Vt output) and Vcc and any GND. Accordingly, please handle the product with care.
2.
The device should not be inserted into or removed from the test apparatus while the voltage is being applied; otherwise breakdown or deterioration in performance of the device may result. Also, avoid any abrupt increasing or decreasing of the voltage. Overshoot or chattering of the power supply may cause the IC to be degraded. To avoid this problem, equip the power supply line with filters.
3.
The peripheral circuits described in this datasheet are given only as system examples for evaluating the performance of the device. Toshiba neither recommend the configuration or related values of the peripheral circuits nor intend to manufacture such application systems in large quantities. Please note that the high-frequency characteristics of the device may vary depending on the external components, mounting method and other factors relating to the application design. Therefore it is the responsibility of users incorporating the device into their designs to evaluate the characteristics of application circuits. Toshiba only guarantee the quality and characteristics of the device as described in this datasheet and do not assume any responsibility for the customer's application design.
4.
In order better to understand the quality and reliability of Toshiba semiconductor products and to incorporate them into designs in an appropriate manner, please refer to the latest Semiconductor Reliability Handbook (Integrated Circuits) published by Toshiba Semiconductor Company. The handbook can also be viewed online at `' http://www.semicon.toshiba.co.jp/ ''
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TA1395FNG Solderability
Regarding solderability, the following conditions have been confirmed. (1) Use of Sn-63Pb solder bath Solder bath temperature = 230C Dipping time = 5 seconds The number Number of times = once Use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder bath Solder bath temperature = 245C Dipping time = 5 seconds Number of times = once Use of R-type flux
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TA1395FNG
RESTRICTIONS ON PRODUCT USE
The information contained herein is subject to change without notice.
030619EBA
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations.
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